Designing and Simulating a New Full Adder with Low Power Consumption
نویسندگان
چکیده
منابع مشابه
A New Low Power Cmos Full Adder
Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates appeared in the literature recently. But they were all designed mostly by intuition and cleverness of the designer. ...
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Full adders are important components in applications such as digital signal processing (DSP) architecture, and microprocessors. Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using adiabatic logic style (DTGAL), which are derived from static CMOS logic, without a large change. This paper also proposes a new design ...
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scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. one of the most promising and possible nano-technologies is cnt (carbon nanotube) based transistors. cnfet have emerged as the more practicable and promising alternative device compared to the other nanotechnologies. this technology has higher efficiency compared to t...
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A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configurati...
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ژورنال
عنوان ژورنال: International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
سال: 2015
ISSN: 2320-3765,2278-8875
DOI: 10.15662/ijareeie.2015.0403002